Design of wireless on-wafer submicron characterization system

A wireless technique for the testing of very large scale ICs and wafers is presented. This test technique uses standard CMOS to achieve wireless parametric testing. This technique has virtually no area overhead, minimal power requirements, and no process or design changes are required. Most compelling is that wafer contact is not required, thereby enabling the in-line process control/monitoring of the manufacture of VLSI wafers or chips. Simulations of representative VLSI antenna designs are presented along with experimental results from the implementation of the antenna coupling and communications link. Also presented are specific circuit simulations showing the characteristics of operation under a range of conditions. The technique is demonstrated experimentally in discrete form with operation at voltages as low as 1 V with submilliwatt power levels. This technique can be implemented with a requirement of 1/10 000th the area of a Pentium-class VLSI circuit, allowing contactless testing of wafers before packaging