A "Flying-Adder" frequency synthesis architecture of reducing VCO stages

Author

Xiu, Liming ; You, Zhihong

Author_Institution

Texas Instrum. Inc., Plano, TX

Volume

13

Issue

2

fYear

2005

Firstpage

201

Lastpage

210

Abstract

The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a voltage-controlled oscillator (VCO) of multiple delay stages. Since the invention of this architecture, various improvements have been made during many implementations of this technique. One of the remaining issues is to reduce the number of delay stages inside the VCO for the benefit of low power consumption and easy design/layout implementation. This paper presents a modified version of the architecture, by utilizing the scalability presented by Xiu and You, 2002, to achieve this goal. The modified architecture can also be used to improve the number of synthesizable frequencies. The tradeoff for this architecture of reduced-delay-stage VCO is the circuit speed

Keywords

adders; circuit layout; delay circuits; frequency synthesizers; voltage-controlled oscillators; circuit design implementation; circuit layout implementation; circuit scalability; circuit speed; flying adder frequency synthesis architecture; multiple delay stage; phase synthesis; power consumption; reduced delay stage VCO; reducing VCO stages; voltage controlled oscillator; Circuit synthesis; Delay; Energy consumption; Frequency locked loops; Frequency synthesizers; Jitter; Phase locked loops; Scalability; Voltage-controlled oscillators; Flying-adder; frequency synthesis; phase-locked loop (PLL); voltage-controlled oscillator (VCO);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2004.840776

Filename

1393021