• DocumentCode
    1232668
  • Title

    TCG: A transitive closure graph-based representation for general floorplans

  • Author

    Lin, Jai-Ming ; Chang, Yao-Wen

  • Author_Institution
    Realtek Semiconductor Corp., Hsinchu, Taiwan
  • Volume
    13
  • Issue
    2
  • fYear
    2005
  • Firstpage
    288
  • Lastpage
    292
  • Abstract
    In this brief, we introduce the concept of the P*-admissible representation and propose a P*-admissible, transitive closure graph-based representation for general floorplans, called transitive closure graph (TCG), and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P*-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying a faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operation, facilitating the convergence to a desired solution. All of these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.
  • Keywords
    VLSI; graph theory; integrated circuit layout; P*-admissible representation; TCG; VLSI design; boundary modules; general floorplans; geometric relation; placement design problems; transitive closure graph-based representation; Circuit topology; Cost function; Design optimization; Performance evaluation; Runtime; Shape; Timing; Tree graphs; Very large scale integration; Wheels; Floorplanning; layout; physical design; transitive closure graph;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2004.840760
  • Filename
    1393028