A Stress-Relaxed Negative Voltage-Level Converter

Author

Tsiatouhas, Yiorgos E.

Author_Institution

Dept. of Comput. Sci., Ioannina Univ.

Volume

54

Issue

3

fYear

2007

fDate

3/1/2007 12:00:00 AM

Firstpage

282

Lastpage

286

Abstract

In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mum triple-well standard CMOS technology, using double-gate-oxide-thickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported

Keywords

CMOS integrated circuits; convertors; voltage control; -3.3 V; 0.18 micron; 0.53 mW; 1.8 V; 1.82 ns; 4.0 V; MOS devices; double-gate-oxide-thickness MOS transistors; embedded negative voltage-level converter; level conversion; level shifter; negative output signal; positive input signal; triple-well standard CMOS technology; voltage stress relaxation; CMOS technology; Circuit simulation; Circuit topology; Delay; Energy consumption; MOS devices; MOSFETs; Power supplies; Stress; Voltage; Embedded negative voltage-level converter; MOS-device voltage stress relaxation; level conversion; level shifter;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.886877

Filename

4132970