• DocumentCode
    123890
  • Title

    Morphable Compression Architecture for Efficient Configuration in CGRAs

  • Author

    Jafri, Syed Mohammad Asad Hassan ; Tajammul, Adeel ; Daneshtalab, Masoud ; Hemani, Ahmed ; Paul, Kolin ; Ellervee, Peeter ; Plosila, Juha ; Tenhunen, Hannu

  • Author_Institution
    Turku Centre for Comput. Sci., Turku, Finland
  • fYear
    2014
  • fDate
    27-29 Aug. 2014
  • Firstpage
    42
  • Lastpage
    49
  • Abstract
    Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads (up to 50% area of the overall platform). As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties (i.e. compression ratio and decoding time), and is therefore best suited for a particular class of applications (and situation). However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to enjoy a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Thereby, our solution offers minimal memory while meeting the required configuration deadlines. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (from configware replication to 52%) and configuration cycles (from 33 nsec to 1.5 secs) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.
  • Keywords
    fast Fourier transforms; matrix multiplication; parallel architectures; reconfigurable architectures; CGRA configuration; FFT; coarse grained reconfigurable architectures; compression/decompression hierarchy; matrix multiplication; morphable compression architecture; runtime parallelism; time sharing; Computer architecture; Decoding; Field programmable gate arrays; Hardware; Multicast communication; Parallel processing; Software; Adaptive systems; CGRAs; Compression; Reconfigurable architectures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design (DSD), 2014 17th Euromicro Conference on
  • Conference_Location
    Verona
  • Type

    conf

  • DOI
    10.1109/DSD.2014.36
  • Filename
    6927225