Generating On-Chip Heterogeneous Systems from High-Level Parallel Code

This work addresses the generation of parallel on-chip heterogeneous systems starting from high-level code with explicit parallelism, based on a custom compiler and a high-level synthesis flow. Blending parallel software programming paradigms with high-level synthesis introduces a range of challenges at both the architectural level and the programming paradigm level, particularly involving the mismatches between the semantics of general high-level parallel code and the coding style imposed by high-level synthesis for FPGAs. We addressed these challenges by introducing some transformations of the source code to adapt it to the underlying hardware synthesis process, and devising a few innovative architectural solutions for supporting OpenMP functionalities. We developed a prototypical toolchain for the generation of heterogeneous hardware/software systems and used it to perform an experimental evaluation of the proposed approach. The results collected from the generated systems exhibit limited performance overheads and high application scalability, confirming the potential impact for the automated synthesis of highly parallel software applications.