Efficient Multiplication on Low-Resource Devices

In this paper, we evaluate various large-integer multiplication methods suitable for resource-constrained devices like passive RFIDs. We restrict our investigations on multi-precision multiplication units in hardware and evaluate their performance regarding area, power, and speed. We implemented and compared different multiplier techniques: array, bit-and digit-serial, Booth, and Karatsuba. We synthesized all designs for a 130 nm low-leakage CMOS process technology. In total, we compared 21 different multipliers with input-word sizes ranging from 8 to 64 bits and having an operating frequency of 1 MHz. The best area-time-power product has been achieved by a 4-bit digit-serial multiplication method. These results are interesting because they have been fairly obtained from a single design flow and by using the same tools. The results can serve as first estimation criterias for forecasting the costs for multiplication-demanding applications running on devices with very limited resources.