• DocumentCode
    1241151
  • Title

    Min-cut replication in partitioned networks

  • Author

    Hwang, L. James ; El Gamal, Abbas

  • Author_Institution
    Inf. Syst. Lab., Stanford Univ., CA, USA
  • Volume
    14
  • Issue
    1
  • fYear
    1995
  • fDate
    1/1/1995 12:00:00 AM
  • Firstpage
    96
  • Lastpage
    106
  • Abstract
    Logic replication has been shown empirically to reduce pin count and partition size in partitioned networks. This paper presents the first theoretical treatment of the min-cut replication problem, which is to determine replicated logic that minimizes cut size. A polynomial time algorithm for determining min-cut replication sets for k-partitioned graphs is derived by reducing replication to the problem of finding a maximum flow. The algorithm is extended to hypergraphs and replication heuristics are proposed for the NP-hard problem with size constraints on partition components. These heuristics, which reduce the worst-case running time by a factor of O(k2) over previous methods, are applied to designs that have been partitioned into multiple FPGA´s. Experimental results demonstrate that min-cut replication provides substantial reductions in the numbers of FPGA´s and pins required
  • Keywords
    circuit layout CAD; computational complexity; field programmable gate arrays; graph theory; logic CAD; logic partitioning; NP-hard problem; hypergraphs; k-partitioned graphs; logic replication; min-cut replication; multiple FPGA; partitioned networks; polynomial time algorithm; replication heuristics; size constraints; Delay; Field programmable gate arrays; Integrated circuit layout; Intelligent networks; Logic arrays; NP-hard problem; Partitioning algorithms; Pins; Polynomials; Senior members;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.363121
  • Filename
    363121