DocumentCode
124116
Title
Improving FPGA accelerated tracking with multiple online trained classifiers
Author
Jacobsen, Matthew ; Sampangi, Siddarth ; Freund, Yoav ; Kastner, Ryan
Author_Institution
Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
fYear
2014
fDate
2-4 Sept. 2014
Firstpage
1
Lastpage
7
Abstract
Robust real time tracking is a requirement for many emerging applications. Many of these applications must track objects even as their appearance changes. Training classifiers online has become an effective approach for dealing with variability in object appearance. Classifiers can learn and adapt to changes online at the cost of additional runtime computation. In this paper, we propose a FPGA accelerated design of an online boosting algorithm that uses multiple classifiers to track and recover objects in real time. Our algorithm uses a novel method for training and comparing pose-specific classifiers along with adaptive tracking classifiers. Our FPGA accelerated design is able to track at 60 frames per second while concurrently evaluating 11 classifiers. This represents a 30× speed up over a CPU based software implementation. It also demonstrates tracking accuracy at state of the art levels on a standard set of videos.
Keywords
field programmable gate arrays; image classification; integrated circuit design; object tracking; real-time systems; CPU based software implementation; FPGA accelerated design; adaptive tracking classifiers; multiple online trained classifiers; object appearance; online boosting algorithm; pose-specific classifiers; robust real time tracking; runtime computation; tracking accuracy; Acceleration; Algorithm design and analysis; Boosting; Field programmable gate arrays; Runtime; Target tracking; Training;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2014 24th International Conference on
Conference_Location
Munich
Type
conf
DOI
10.1109/FPL.2014.6927505
Filename
6927505
Link To Document