DocumentCode
1243707
Title
Performance analysis of finite-buffered asynchronous multistage interconnection networks
Author
Mohapatra, Prasant ; Das, Chita R.
Author_Institution
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume
7
Issue
1
fYear
1996
fDate
1/1/1996 12:00:00 AM
Firstpage
18
Lastpage
25
Abstract
We present a queueing model for performance analysis of finite-buffered multistage interconnection networks. The proposed model captures network behaviour in an asynchronous communication mode and is based on realistic assumptions. A uniform traffic model is developed first and then extended to capture nonuniform traffic in the presence of a hot-spot. Throughput and delay are computed using the proposed model and the results are validated via simulation. The analysis is extended to predict performance of MIN-based multiprocessors. The effects of buffer length, switch size, and the maximum allowable outstanding requests on the system performance are discussed. Various design decisions using this model are drawn with respect to delay, throughput, and system power
Keywords
buffer storage; delays; multistage interconnection networks; packet switching; performance evaluation; queueing theory; virtual machines; MIN-based multiprocessors; asynchronous communication mode; buffer length effect; delay; design decisions; finite-buffered asynchronous multistage interconnection networks; hot spot; maximum allowable outstanding requests; network behaviour; nonuniform traffic; performance analysis; queueing model; simulation; switch size effect; system power; throughput; uniform traffic model; Asynchronous communication; Computational modeling; Delay; Multiprocessor interconnection networks; Performance analysis; Queueing analysis; Switches; Telecommunication traffic; Throughput; Traffic control;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/71.481594
Filename
481594
Link To Document