On-chip power-supply network optimization using multigrid-based technique

In this paper, we present a novel multigrid-based technique for the problem of on-chip power-supply network optimization. The multigrid-based technique is applied to reduce a large-scale network to a much coarser one. The reduced network can be efficiently optimized. The solution for the original network is then quickly computed using a back-mapping process. Due to the adoption of an accurate resistance-inductance-capacitance power-supply network and time-varying switching-current model, our technique is capable of optimizing power grid and decoupling capacitance simultaneously. Experimental results show that large-scale power-supply networks with millions of nodes can be solved in a few minutes. The proposed technique not only speeds up significantly the optimization process, without compromising the quality of solutions, but also brings up a possibility of incorporating the power-supply network optimization into other physical design stages such as signal routing.