Efficient and effective placement for very large circuits

Author

Sun, Wern-Jieh ; Sechen, Carl

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA

Volume

14

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

349

Lastpage

359

Abstract

We present a new approach to simulated annealing and a new hierarchical algorithm for row-based placement which has obtained the best results ever reported for a large set of MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are achieved compared with TimberWolfSC v6.0. Our new hierarchical annealing-based placement algorithm (TimberWolfSC v7.0) yields chip area reductions up to 21% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. Furthermore, TimberWolfSC v7.0 produces lower total wire length by an average of 8% than Gordian/Domino, 11% lower wire length than Ritual/Tiger, while using comparable run time. TimberWolfSC v7.0 also supports precise timing driven placement

Keywords

cellular arrays; circuit layout CAD; circuit optimisation; integrated circuit layout; integrated logic circuits; logic CAD; logic design; network routing; simulated annealing; CPU time; MCNC benchmark circuits; TimberWolfSC; chip area reductions; hierarchical algorithm; row-based placement; simulated annealing; timing driven placement; total wire length; Central Processing Unit; Circuit simulation; Circuit synthesis; Computer errors; Hip; Quadratic programming; Simulated annealing; Sun; Timing; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.365125

Filename

365125