Timing models for gallium arsenide direct-coupled FET logic circuits

Author

Kayssi, Ayman I. ; Sakallah, Karem A.

Author_Institution

Dept. of Electr. Eng., American Univ. of Beirut, Lebanon

Volume

14

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

384

Lastpage

393

Abstract

In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional analysis aimed at finding suitable minimal functional forms that capture the effects of all relevant parameters. The process is illustrated through a detailed step-by-step account of the macromodel development for DCFL inverters. Based on different modeling approximations, one- and two-argument macromodel functions are derived and compared. The inverter macromodel is then used as a basis for developing timing macromodels for superbuffers and NOR gates. The NOR gate macromodels account for the simultaneous and near-simultaneous switching of two inputs, with an extension to multiple inputs

Keywords

III-V semiconductors; MESFET integrated circuits; circuit CAD; delays; direct coupled FET logic; field effect logic circuits; gallium arsenide; integrated circuit design; integrated circuit modelling; logic CAD; logic gates; timing; NOR gates; delay time; dimensional analysis; direct-coupled FET logic circuits; macromodels; minimal functional forms; modeling approximations; near-simultaneous switching; superbuffers; timing models; transition time; CMOS logic circuits; Capacitance; Delay effects; Delay estimation; FETs; Gallium arsenide; Inverters; Logic circuits; MOS devices; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.365129

Filename

365129