A row-based cell placement method that utilizes circuit structural properties

We propose a cell placement method for row-based integrated circuit layout. The proposed method cleverly utilizes the structural properties of the circuits. It first extracts strongly connected subcircuits, called cones, from the circuit and then groups small cones, called fragments, to reduce the number of cones. The algorithm then performs a macro-cell placement, treating each cone as a soft macro. Next, it maps the resulting macro-cell placement into a row-based placement. Finally, it applies a simulated-annealing procedure to refine the row-based placement. It is able to produce, in a shorter period of CPU time, a higher quality placement compared to classical simulated-annealing-based placement methods as demonstrated by some experimental results on the MCNC benchmarks