• DocumentCode
    1245490
  • Title

    An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories

  • Author

    Neuberger, Gustavo ; De Lima, Fernanda Gusmão Kastensmidt ; Reis, Ricardo

  • Author_Institution
    Fed. Univ. of Rio Grande do Sul, Brazil
  • Volume
    22
  • Issue
    1
  • fYear
    2005
  • Firstpage
    50
  • Lastpage
    58
  • Abstract
    Modern SoC architectures manufactured at ever-decreasing geometries use multiple embedded memories. Error detection and correction codes are becoming increasingly important to improve the fault tolerance of embedded memories. This article focuses on automatically optimizing classical Reed-Solomon codes by selecting the appropriate code polynomial and set of used symbols.
  • Keywords
    Reed-Solomon codes; digital storage; embedded systems; error correction codes; error detection codes; fault tolerant computing; multiplying circuits; system-on-chip; Reed-Solomon codes; SoC architecture; embedded SRAM memories; error correction codes; error detection codes; fault tolerance techniques; multipliers; Arithmetic; Error correction codes; Fault tolerance; Galois fields; Geometry; Iterative algorithms; Iterative decoding; Manufacturing; Polynomials; Reed-Solomon codes;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2005.2
  • Filename
    1401824
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1245490