Modeling ESD protection

This work presents the modeling and simulation of ESD circuit design protection. The electrostatic discharge (ESD) is a charge rebalancing process between two adjacent ICs. The ESD can cause IC failure during the manufacturing, the testing, the handling and the assembly of integrated circuits (ICs). ESD protection design methodology needs to be as systematic and transferable as possible. The empirical, trial and error method for creating ESD protection schemes is based on fabricating several test protection structures, gradually applying increasing voltage pulses and then measuring the functionality of the protection structures. This method is time consuming and destructive in nature. The model could be used to optimize the ESD circuit´s design and predict its protection performance. A combination of bias conditions and layout parameters could maximize the ESD robustness device. This optimization can be achieved by developing simulation tools for ESD circuits. ESD is a phenomenon that causes reliability problems and even permanent damages to the IC since the goal is to find the voltage and the current limits before the device fails permanently.