A LOG-EXP still image compression chip design

Author

Huang, Sheng-Chieh ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

45

Issue

3

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

812

Lastpage

819

Abstract

A fully pipelined single chip is proposed for the LOG-EXP still image compression. The design of the LOG-EXP image compression system focuses on the high compression ratio of the complex texture (e.g. benchmark image baboon) and high quality image, especially for the PSNR requirement above 36. In comparison with the JPEG compression result (bpp=0.99 and PSNR=26.9), this compression algorithm uses less bpp (bpp=0.87) to get a higher image quality (PSNR=36.38) for the benchmark image baboon. The entire LOG-EXP image compression system can be implemented on a single chip to yield a clock rate of 175 MHz which allow an input rate of 30 frames per second for 1024×1024 color images

Keywords

data compression; digital signal processing chips; image coding; image texture; pipeline processing; 175 MHz; GSM electronic road map; JPEG compression; LOG-EXP still image compression chip; PSNR; VLSI architecture; benchmark image; clock rate; color images; complex texture; compression algorithm; digital TV; fame-based digital still camera image; high compression ratio; high quality image; image/video DSP coprocessor; input rate; pipelined single chip design; single chip; Chip scale packaging; Image coding; Image quality; Multimedia systems; PSNR; Pixel; Programmable logic arrays; Transform coding; Video compression; Videoconference;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.793613

Filename

793613