An automatic gain control architecture for SONET OC-3 VLSI

Author

Wang, Chorng-Kuang ; Huang, Po-Chiun

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Volume

44

Issue

9

fYear

1997

fDate

9/1/1997 12:00:00 AM

Firstpage

779

Lastpage

783

Abstract

This work presents a synchronized feedback-type automatic gain control (AGC) architecture for SONET (synchronous optical network) OC-3 system which is suitable for scaled BJT or CMOS VLSI implementation. In this architecture, a second-order loop is utilized instead of a conventional loop, and a convenient methodology is presented for calculating the parameters of the AGC. Simulation results using micromodels in the HSPICE environment indicate that for a 20 dB dynamic range of input 77.76 MHz sinusoidal signal, the architecture yields an 80 kHz loop bandwidth and a constant 1 V_pp output magnitude

Keywords

CMOS integrated circuits; SONET; VLSI; automatic gain control; bipolar integrated circuits; circuit feedback; digital communication; optical communication equipment; optical fibre networks; 1 V; 155.52 Mbit/s; 77.76 MHz; 80 kHz; CMOS VLSI implementation; HSPICE environment; SONET OC-3 VLSI; automatic gain control architecture; micromodels; scaled BJT VLSI implementation; second-order loop; synchronized feedback-type AGC; synchronous optical network; Circuit noise; Cutoff frequency; Digital filters; Gain control; Noise reduction; Passband; SONET; Signal processing; Transfer functions; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.625022

Filename

625022