• DocumentCode
    1253486
  • Title

    VLSI module placement based on rectangle-packing by the sequence-pair

  • Author

    Murata, Hiroshi ; Fujiyoshi, Kunihiro ; Nakatake, Shigetoshi ; Kajitani, Yoji

  • Author_Institution
    Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
  • Volume
    15
  • Issue
    12
  • fYear
    1996
  • fDate
    12/1/1996 12:00:00 AM
  • Firstpage
    1518
  • Lastpage
    1524
  • Abstract
    The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement
  • Keywords
    VLSI; circuit layout CAD; circuit optimisation; integrated circuit design; modules; simulated annealing; wiring; MCNC benchmark; VLSI module placement; ami49; finite solution space; layout; module name sequences; physical design; rectangle-packing; sequence-pair; simulated annealing; wiring area estimation method; Circuits; Costs; Genetic algorithms; Information science; Polynomials; Production; Simulated annealing; Very large scale integration; Wiring;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.552084
  • Filename
    552084