• DocumentCode
    1255574
  • Title

    Developing a 0.18-micron CMOS process

  • Author

    Haond, M. ; Basso, M.-T. ; Lair, C.

  • Author_Institution
    Centre Commun CNET-STMicroelectron., Crolles
  • Volume
    19
  • Issue
    5
  • fYear
    1999
  • Firstpage
    16
  • Lastpage
    22
  • Abstract
    The authors discuss ways to develop certain modules that are required to generate a new generation of devices and meet targeted goals. They also introduce the integration of low-k material to improve IMD parasitic capacitance
  • Keywords
    CMOS integrated circuits; integrated circuit technology; 0.18 micron; 0.18-micron CMOS process; IMD parasitic capacitance; integrated circuit manufacture; CMOS integrated circuits; CMOS process; CMOS technology; Implants; MOS devices; Manufacturing industries; Manufacturing processes; Parasitic capacitance; Threshold voltage; Transistors;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.798105
  • Filename
    798105
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1255574