Optimising accelerator for CAD workstation

Sequential versions of those optimisation algorithms which are based on random search heuristics are often too slow to be of value to the interactive user of a CAD workstation. A significant gain in speed can be achieved by using concurrent algorithms to drive an optimising accelerator attached to the workstation. The paper discusses the design and performance of a hardware accelerator which incorporates INMOS transputers. Concurrent versions of two algorithms are described, one relevant to combinatorial optimisation and the other to global optimisation. The mapping of these algorithms on to the transputer hardware is discussed. The application and performance of each algorithm is illustrated by means of a representative problem from the field of electronic engineering.