DocumentCode
1255829
Title
Permutation realizability and fault tolerance property of the inside-out routing algorithm
Author
Seo, Seung-Woo ; Feng, Tse-yun ; Lee, Hyoung-Il
Author_Institution
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Volume
10
Issue
9
fYear
1999
fDate
9/1/1999 12:00:00 AM
Firstpage
946
Lastpage
957
Abstract
In this paper, we analyze ways of realizing permutations in a class of 2log2N- or (2log2N-1)-stage rearrangeable networks. The analysis is based on the newly developed inside-out routing algorithm and we derive the upper and lower bounds on the number of possible realizations of a permutation. It is shown that the algorithm can provide us with comparable degrees of freedom in realizing a given permutation as the well-known looping algorithm, while it can be more generally applied to a class of 2log2N- or (2log2 N-1)-stage rearrangeable networks. In finding a set of complete assignments for the center-stage cycles, alternate realizations of a permutation can be obtained by changing the initial position, changing the assigning direction, or even interchanging the first-level decompositions of the permutation. We also show that these numerable alternate realizations can be utilized to make the networks tolerate some sets of faults, i.e., control faults of SEs including stuck-at-straight and stuck-at-cross. Various cases of single control faults at the center stages and other stages are examined through examples. These new approaches originate from routing outward from center stages to outer stages; therefore, the center stages and two half networks may be treated separately
Keywords
fault tolerant computing; multiprocessor interconnection networks; network routing; reconfigurable architectures; fault tolerance property; inside-out routing algorithm; lower bounds; permutation realizability; rearrangeable networks; stuck-at-cross; stuck-at-straight; upper bounds; Algorithm design and analysis; Bandwidth; Communication switching; Computer networks; Fault tolerance; Fault tolerant systems; Feedback; Multiprocessor interconnection networks; Routing; Switches;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/71.798318
Filename
798318
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