Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation of under 0.7 V

Author

Yagishita, Atsushi ; Saito, Tomohiro ; Inuniiya, S. ; Matsuo, Kouji ; Tsunashima, Yoshitaka ; Suguro, Kyoichi

Author_Institution

Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan

Volume

49

Issue

3

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

422

Lastpage

428

Abstract

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V)

Keywords

CMOS integrated circuits; MOSFET; integrated circuit metallisation; low-power electronics; semiconductor device metallisation; work function; 0.7 V; Al-TiN; Al/TiN gate; CMOS transistors; CMP; Si; W-TiN; W/TiN gate; chemical mechanical polishing; counter doping; damascene metal gate MOSFET technology; dynamic threshold-voltage; high drive current; high-k gate dielectric; midgap work function metal gates; subthreshold swing; uniform electrical characteristics; very low voltage operation; Counting circuits; Degradation; Dielectrics; Electrodes; Joining processes; Low voltage; MOSFET circuits; Silicon; Threshold voltage; Tin;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.987112

Filename

987112