CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range

To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultra high operation speeds up to 208 GHz, with ultra wide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed X range)/power in GHz²/mW] is roughly an order of magnitude higher than that of the state of the art.