Nanoscale and Device Level Gate Conduction Variability of High-k Dielectrics-Based Metal-Oxide-Semiconductor Structures

The polycrystalline microstructure of the high-k dielectric of gate stacks in metal-oxide-semiconductor (MOS) devices can be a potential source of variability. In this paper, a conductive atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) have been used to investigate how the thickness and the crystallization (after a thermal annealing) of the high-k layer affect the nanoscale morphological and electrical properties of the gate stack. The impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices has also been investigated.