DocumentCode
1263109
Title
Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)
Author
Lau, John H. ; Lee, Shi-Wei Ricky
Author_Institution
Agilent Technol., San Jose, CA, USA
Volume
25
Issue
1
fYear
2002
fDate
3/1/2002 12:00:00 AM
Firstpage
3
Lastpage
14
Abstract
The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer
Keywords
chip scale packaging; creep; printed circuit manufacture; reliability; soldering; Garofalo-Arrhenius constitutive law; Sn-Ag-Pb; creep; microvia build-up layer; printed circuit board; shear stress; solder joint reliability; thermal cyclic loading; thermal expansion coefficient; thermomechanical characteristics; wafer level chip scale package; Assembly; Capacitive sensors; Chip scale packaging; Creep; Hysteresis; Printed circuits; Soldering; Thermal loading; Thermal stresses; Wafer scale integration;
fLanguage
English
Journal_Title
Components and Packaging Technologies, IEEE Transactions on
Publisher
ieee
ISSN
1521-3331
Type
jour
DOI
10.1109/6144.991169
Filename
991169
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