Miniature 3-D inductors in standard CMOS process

Author

Tang, Chih-Chun ; Wu, Chia-Hsin ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

37

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

471

Lastpage

480

Abstract

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f_SR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q_max. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced

Keywords

CMOS analogue integrated circuits; Q-factor; UHF amplifiers; UHF integrated circuits; inductance; inductors; 0.35 micron; 2.4 GHz; CMOS LNA; CMOS low-noise amplifier; digital one-poly-four-metal CMOS process; inductance; maximum quality factor; miniature 3D inductors; radio frequency chip cost reduction; self-resonance frequency; standard CMOS process; three-dimensional inductor; CMOS process; Costs; Frequency measurement; Inductance; Inductors; Low-noise amplifiers; Q factor; Radio frequency; Spirals; Strontium;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.991385

Filename

991385