Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers

Author

Rosselló, José Luis ; Segura, Jaume

Author_Institution

Dept. de Fisica, Univ. de les Illes Baleares, Palma de Mallorca, Spain

Volume

21

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

433

Lastpage

448

Abstract

The authors present an accurate analytical method for analyzing the power consumption in CMOS buffers. It is derived from the charge transferred through the circuit and makes use of the physically based MM9 MOSFET model (Velghe et al., 1994), (Foty et al., 1997) as well as a modified Sakurai alpha-power law model. The resulting analytical model accounts for the effects of input slew time, device sizes, carrier velocity saturation effects, input-to-output coupling capacitance, output load, and temperature. Results are compared to HSPICE simulations (level 50) and to other models previously published considering a large set of parameters for a 0.18 and 0.35 μm technologies, showing significant improvements

Keywords

CMOS logic circuits; buffer circuits; capacitance; carrier mobility; circuit simulation; integrated circuit modelling; logic simulation; low-power electronics; 0.18 micron; 0.35 micron; carrier velocity saturation effects; charge-based analytical model; device sizes; input slew time; input-to-output coupling capacitance; modified Sakurai alpha-power law model; output load; physically based MM9 MOSFET model; power consumption; submicron CMOS buffers; temperature; Analytical models; Capacitance; Conductivity; Doping; Energy consumption; MOS devices; MOSFET circuits; Semiconductor device modeling; Threshold voltage; Voltage control;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.992767

Filename

992767