High-performance 64-bit binary comparator

Author

Anjuli ; Anand, Sruthy

Author_Institution

FET, E&CE Dept., MITS, Sikar, India

fYear

2014

fDate

6-8 Feb. 2014

Firstpage

512

Lastpage

519

Abstract

High-performance 64-bit binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This briefly presents comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption and delay. Means some modifications have been done in existing 64-bit binary comparator design to improve the performance of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 90nm technology in Tanner EDA Tool.

Keywords

comparators (circuits); digital arithmetic; electronic design automation; performance evaluation; 90nm technology; Tanner EDA tool; basic arithmetic operation; circuit performance improvement; comparison operation; delay; digital arithmetic; high-performance 64-bit binary comparator designs; power consumption; CMOS integrated circuits; Logic gates; Binary comparator; digital arithmetic; high-speed; low- power;

fLanguage

English

Publisher

ieee

Conference_Titel

Optimization, Reliabilty, and Information Technology (ICROIT), 2014 International Conference on

Conference_Location

Faridabad

Print_ISBN

978-1-4799-3958-9

Type

conf

DOI

10.1109/ICROIT.2014.6798377

Filename

6798377