A testable CMOS synchronous counter

A testable design of a CMOS synchronous counter is presented with test vectors that provide 100% coverage of stuck-at and stuck-open faults in a time of order L², where L is the bit length of the counter. This design is made compatible with the scan design methodology by incurring minimal hardware overhead which is also fully testable for the above faults. Test application time is shown to be strongly dependent on observability of the counter outputs and can be considerably reduced if the outputs are directly observable without having to scan the test results out. The authors develop a signal flow model for the counter, based on which, test vectors are derived and proved to provide complete coverage of the above faults. The design is also superior in that its operating speed is only limited by a single inverter delay, found to be 1-4 ns per bit slice, depending on the CMOS process. Furthermore, this speed is not affected by the addition of scan circuitry