A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design

Author

Wang, Kanwen ; Chen, Jialin ; Cao, Wei ; Wang, Ying ; Wang, Lingli ; Tong, Jiarong

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

Volume

58

Issue

7

fYear

2011

fDate

7/1/2011 12:00:00 AM

Firstpage

432

Lastpage

436

Abstract

This brief presents a reconfigurable VLSI architecture which is designed for multi-transform codec in several video coding standards of MPEG-2/4, VC-1, H.264/AVC and AVS. The reconfigurable multiple constant multiplication algorithm with two fusing strategies is provided to generate constant multipliers in the matrix calculation blocks. Additionally, adder-sharing strategy is adopted in the unified preprocessing/postprocessing block to save circuit areas. The proposed architecture can support different standards through static reconfiguration and forward/inverse transform functions through dynamic reconfiguration. It is suitable for the real-time processing of 1080P HD video codec with six video standards transforms.

Keywords

VLSI; adders; inverse transforms; logic CAD; matrix algebra; multiplying circuits; real-time systems; reconfigurable architectures; video codecs; video coding; 1080P HD video codec; AVS; H.264/AVC; MPEG-2/4; VC-1; adder-sharing strategy; constant multipliers; dynamic reconfiguration; forward transform functions; fusing strategy; inverse transform functions; matrix calculation blocks; multitransform codec; postprocessing block; preprocessing block; real-time processing; reconfigurable VLSI architecture; reconfigurable multiple constant multiplication algorithm; reconfigurable multitransform VLSI architecture; six video standards transforms; static reconfiguration; video codec design; video coding standards; Adders; Computer architecture; Discrete cosine transforms; Standards; Transform coding; Very large scale integration; Adder-sharing; computer-aided design (CAD); dynamic reconfiguration; multi-transform; reconfigurable multiple constant multiplication (RMCM); static reconfiguration;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2011.2158265

Filename

5951748