Analysis of dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for on-chip cache

Author

Hamzaoglu, Fatih ; Ye, Yibin ; Keshavarzi, Ali ; Zhang, Kevin ; Narendra, Siva ; Borkar, Shekhar ; Stan, Mircea ; De, Vivek

Author_Institution

Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA

Volume

10

Issue

2

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

91

Lastpage

95

Abstract

This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

Keywords

MOS memory circuits; SRAM chips; VLSI; cache storage; cellular arrays; circuit simulation; circuit stability; leakage currents; 0.13 micron; active leakage power; cell area; dual-V/sub T/ SRAM cells; full-swing single-ended bit line sensing; low-V/sub T/ peripheral circuits; minimum channel length pass transistors; noise recovery; on-chip cache; single-ended sensing; Circuit noise; Circuit stability; Degradation; Delay lines; Differential amplifiers; Microprocessors; Paper technology; Performance gain; Random access memory; Voltage;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.994983

Filename

994983