DocumentCode
1271474
Title
PACE: a regular array for implementing regularly and irregularly structured algorithms
Author
Spray, A. ; Jones, S.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Newcastle Univ., NSW, Australia
Volume
138
Issue
5
fYear
1991
fDate
10/1/1991 12:00:00 AM
Firstpage
613
Lastpage
619
Abstract
The programmable adaptive computing engine (PACE), a medium-grained cellular automaton-based architecture supporting regularly and irregularly structured functions within a regularly structured array, is introduced. The PACE philosophy is described in detail. Its flexibility is demonstrated through the embedment of three irregularly structured algorithms within the PACE environment. Some results obtained from an investigation into processor granularity are presented to assess the size and performance of the PACE family of processors
Keywords
VLSI; parallel processing; systolic arrays; PACE family of processors; PACE philosophy; cellular automaton-based architecture; irregularly structured algorithms; irregularly structured functions; medium-grained; performance; processor granularity; programmable adaptive computing engine; regularly structured array;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
99510
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