Explicit formulation of delays in CMOS data paths

Author

Deschacht, D. ; Robert, M. ; Auvergne, D.

Author_Institution

Lab. d´´Autom. et de Microelectron. de Montpellier, Univ. des Sci. et Techn. du Languedoc, France

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1257

Lastpage

1264

Abstract

An explicit formulation of the transient response of general combinational CMOS structures is presented, including load conditions and driving waveforms. Based on data-path decomposition in unidirectional elementary cells, timing models developed here allow an analytic formulation of the real temporal behaviour of inverters, transmission gate arrays, and general CMOS gates. Validation is obtained through a comparison between delay times, calculated following this formulation, and values deduced from SPICE simulations, for a large range of inverters and gate structures with different configuration ratios and tapering factors. Results are shown to be in excellent agreement with less than 10% discrepancy

Keywords

CMOS integrated circuits; digital integrated circuits; digital simulation; logic CAD; CMOS data paths; SPICE simulations; analytic formulation; combinational CMOS structures; configuration ratios; data-path decomposition; delay times; driving waveforms; explicit formulation; general CMOS gates; inverters; load conditions; real temporal behaviour; tapering factors; timing models; transient response; transmission gate arrays; unidirectional elementary cells; Circuits; Delay effects; Inverters; Macrocell networks; Parasitic capacitance; Propagation delay; SPICE; Silicon; Timing; Transient response;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5953

Filename

5953