Error suppressing encode logic of FCDL in a 6-b flash A/D converter

Author

Ono, Koichi ; Matsuura, Tatsuji ; Imaizumi, Eiki ; Okazawa, Hisashi ; Shimokawa, Ryuushi

Author_Institution

Semiconductor & Integrated Circuit Div., Hitachi Ltd., Tokyo, Japan

Volume

32

Issue

9

fYear

1997

fDate

9/1/1997 12:00:00 AM

Firstpage

1460

Lastpage

1464

Abstract

A 6-b, 166-Ms/s BiCMOS flash A/D converter was fabricated using a folded cascoded differential logic (FCDL). This FCDL reduces glitch errors caused by comparator metastability and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7-μm, f _t=12 GHz BiCMOS was less than 10^-10 times/sample. Without power-consuming highspeed track and hold circuit, the FCDL achieved low error rate and low power consumption of 505 mW at a 5.0-V power supply

Keywords

BiCMOS integrated circuits; analogue-digital conversion; comparators (circuits); 0.7 micron; 12 GHz; 5.0 V; 505 mW; 6 bit; BiCMOS; comparator metastability; encoder operation speed; error rates; error suppressing encode logic; flash A/D converter; folded cascoded differential logic; glitch errors; power consumption; BiCMOS integrated circuits; Circuit noise; Encoding; Error analysis; Logic; Metastasis; Reflective binary codes; Semiconductor device measurement; Semiconductor device noise; Signal to noise ratio;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.628765

Filename

628765