Enhanced sampling clock offset correction based on time domain estimation scheme

This paper is concerned with the issue of sampling clock synchronization and correction. First, we make an analysis of the cause of the sampling clock offset and its effect on the performance of communication systems. A novel time domain-based sampling clock offset estimation method is proposed with greatly decreased estimation delay time. A sampling clock adjusting model in time domain is proposed as well. Simulations and numerical analysis verify better mean square error performance of the proposed method and adjusting model in contrast to the conventional sampling clock synchronization methods. In addition, three types of methods to further improve the sampling clock offset estimation accuracy in burst packet transmission systems are simulated and analyzed with some conclusions drawn.