Neuro-fuzzy architecture for CMOS implementation

Author

Wilamowski, Bogdan M. ; Jaeger, Richard C. ; Kaynak, M. Okyay

Author_Institution

Dept. of Electr. Eng., Wyoming Univ., Laramie, WY, USA

Volume

46

Issue

6

fYear

1999

fDate

12/1/1999 12:00:00 AM

Firstpage

1132

Lastpage

1136

Abstract

In this paper, a nonconventional structure for a “fuzzy” controller is proposed. It does not require signal division, and it produces control surfaces similar to classical fuzzy controllers. The structure combines fuzzification, MIN operators, normalization, and weighted sum blocks. The fuzzy architecture is implemented as a VLSI chip using 2-μm n-well technology. A new fuzzification circuit, which requires only one differential pair per membership function is proposed. Eight equally spaced membership functions are used in the VLSI implementation. Simple voltage MIN circuits are used for rule selection. A modified Takagi-Sugeno approach with normalization and weighted sum is used in the defuzzification circuit. Weights in the defuzzifier are digitally programmable with 6-bits resolution

Keywords

CMOS integrated circuits; VLSI; control system synthesis; fuzzy control; neurocontrollers; 2 mum; CMOS implementation; MIN operators; VLSI chip; VLSI implementation; classical fuzzy controllers; control surfaces; defuzzification circuit; digitally programmable weights; equally spaced membership functions; fuzzification circuit; fuzzy architecture; fuzzy controller; membership function; modified Takagi-Sugeno approach; neuro-fuzzy architecture; normalization; rule selection; weighted sum; weighted sum blocks; Circuits; Fuzzy control; Fuzzy systems; Helium; MOSFETs; Signal processing; Signal resolution; Space technology; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Industrial Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0278-0046

Type

jour

DOI

10.1109/41.808001

Filename

808001