DocumentCode
1276615
Title
Hardware Accelerated Impairment-Aware Control Plane for Future Optical Networks
Author
Qin, Yixuan ; Azodolmolky, Siamak ; Gunkel, Matthias ; Nejabati, Reza ; Simeonidou, Dimitra
Author_Institution
Sch. of CSEE, Univ. of Essex, Colchester, UK
Volume
15
Issue
9
fYear
2011
fDate
9/1/2011 12:00:00 AM
Firstpage
1004
Lastpage
1006
Abstract
In this letter, a hardware accelerated GMPLS based and impairment-aware control plane suitable for optical networks with concurrent lightpath requests support is proposed and evaluated. It outperforms the software version by 80 times in the order of sub-seconds. The high acceleration rate, simultaneous requests support, scalability and low computation time variance are the key features of this tool.
Keywords
concurrency control; field programmable gate arrays; multiprotocol label switching; optical fibre networks; FPGA; concurrent lightpath request support; future optical networks; hardware accelerated GMPLS; hardware accelerated impairment-aware control plane; Acceleration; Estimation; Field programmable gate arrays; Hardware; Optical fiber networks; Pipelines; Software; Control plane; FPGA; Q factor; hardware accelerator; impairment aware; optical networking;
fLanguage
English
Journal_Title
Communications Letters, IEEE
Publisher
ieee
ISSN
1089-7798
Type
jour
DOI
10.1109/LCOMM.2011.070711.110410
Filename
5958550
Link To Document