Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs

The efficient and successful realization of low-power semiconductor devices demands, among other things, the ability to quantitatively model and minimize myriad leakage phenomena. We report herein a general physical model to quantitatively compute crystallographic-orientation-dependent gate-induced drain leakage (GIDL), and its numerical implementation in a continuum-based device simulator. This simulation model has been successfully compared with relevant experimental data derived from heavily doped vertical diodes and 45-nm silicon-based CMOS devices. Also, the process optimization of next-generation 32-nm low-power devices has been discussed in the context of GIDL.