Design and performance analysis of reversible logic based ALU using hybrid single electron transistor

Author

Jana, Biswabandhu ; Jana, Anindya ; Basak, S. ; Sing, Jamuna Kanta ; Sarkar, Subir Kumar

Author_Institution

Dept. of Electron. & Telecommun. Eng., Jadavpur Univ., Kolkata, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

4

Abstract

The Co-integration of SET (Single Electron Transistor) and CMOS is the new evolution for the stunning growth in modern semiconductor industry. In the present work we have demonstrated that the successful implementation of ALU (Arithmetic Logic Unit) using hybrid SET-CMOS and hybrid SET-CMOS based Reversible logic gates. We have represented the simulation output of the both cases and a comparison has made between different design methods. The experimental delay measurement has also been presented. All the simulations are done using Hybrid SET-CMOS technology with the help of MIB and BSIM4.6.1 model in tanner environment to realize the better performance.

Keywords

CMOS digital integrated circuits; integrated circuit design; logic gates; single electron transistors; ALU; BSIM4.6.1 model; CMOS based reversible logic gates; MIB model; SET cointegration; arithmetic logic unit; delay measurement; design methods; hybrid single electron transistor; modern semiconductor industry; performance analysis; tanner environment; Adders; CMOS integrated circuits; Delays; Hybrid power systems; Logic gates; Multiplexing; Power demand; ALU; BSIM4.6.1; Hybrid SET; MIB; Reversible logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Computational Sciences (RAECS), 2014 Recent Advances in

Conference_Location

Chandigarh

Print_ISBN

978-1-4799-2290-1

Type

conf

DOI

10.1109/RAECS.2014.6799652

Filename

6799652