DocumentCode
1285763
Title
Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory
Author
Fang, Hongxia ; Chakrabarty, Krishnendu ; Wang, Zhiyuan ; Gu, Xinli
Author_Institution
Cadence Design Syst., Endicott, NY, USA
Volume
31
Issue
10
fYear
2012
Firstpage
1586
Lastpage
1599
Abstract
Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases-suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in a ranked order. We propose a new method based on dataflow analysis and Dempster-Shafer (DS) theory for ranking faulty blocks in the first phase of diagnosis. The proposed approach transforms the information derived from one functional test failure into multiple-stage failures by partitioning the given functional test into multiple stages. A measure of “belief” is then assigned to each block based on the knowledge of each failing stage, and the DS theory is subsequently used to aggregate the beliefs from multiple failing stages. Blocks with higher beliefs are ranked on the top of the candidate list. Simulations on an industry design for a network interface application as well as on an open source system-on-a-chip show that the proposed method can provide accurate ranking for most board-level functional failures.
Keywords
data flow analysis; electronic engineering computing; fault diagnosis; integrated circuit testing; system-on-chip; uncertainty handling; DS theory; Dempster-Shafer theory; board-level functional failure diagnosis; dataflow analysis; fault diagnosis; faulty block ranking; faulty component; fine-grained diagnosis; functional test failure; industry design; multiple-stage failures; network interface; open source system-on-a-chip; uncertainty; Adaptation models; Circuit faults; Clocks; Industries; Integrated circuit modeling; Optimization; Reliability; Board-level; Dempster–Shafer (DS) theory; dataflow analysis; diagnosis; functional failure;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2012.2198884
Filename
6303933
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