DocumentCode
128862
Title
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures
Author
Martins, Rui P. ; Lourenco, Nuno ; Canelas, Antonio ; Horta, Nuno
Author_Institution
Inst. de Telecomun., Tech. Univ. Lisbon, Lisbon, Portugal
fYear
2014
fDate
24-28 March 2014
Firstpage
1
Lastpage
6
Abstract
This paper describes an electromigration-aware and IR-Drop avoidance routing approach considering multiport multiterminal (MP/MT) signal nets of analog integrated circuits (IC). The effects of current densities and temperature in the interconnects may cause the malfunction/failure of a circuit due to IR-Drop or electromigration (EM). These become increasingly more relevant with the ongoing reduction of circuit sizes caused by the evolution of the nanoscale integration processes. Therefore, EM and IR-Drop effects must be taken into account in the design of both power networks and signal wires of analog and mixed-signal ICs, to make their impact on the circuits´ reliability negligible. In previous EM and IR-Drop-aware analog IC routing approaches, `dot-models´ are assumed for the terminals, i.e., each terminal has only one port that need to be routed, however, in practice, analog standard cells usually contain multiple electrically-equivalent locations, often distributed over different fabrications layers, where legal connections can be made, i.e., MP terminals, which need to be properly explored. The design flow is detailed, and the applicability of the approach is demonstrated with experimental results, and also, by generating the routing of an analog circuit structure for the UMC 130 nm design process.
Keywords
analogue integrated circuits; current density; electromigration; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; network routing; EM-aware routing approach; IR-Drop avoidance routing approach; MP terminals; MP-MT signal nets; UMC design process; analog IC; analog circuit structure; analog integrated circuits; analog multiport terminal structures; analog standard cells; circuit failure; circuit malfunction; circuit reliability; circuit size reduction; current density; design flow; dot-models; electrically-equivalent locations; electromigration-aware routing approach; fabrication layer; interconnects; legal connections; mixed-signal IC; multiport multiterminal signal nets; nanoscale integration process; power networks; signal wires; Current density; Layout; Nonhomogeneous media; Ports (Computers); Routing; Steiner trees; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location
Dresden
Type
conf
DOI
10.7873/DATE.2014.023
Filename
6800224
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