• DocumentCode
    128878
  • Title

    Energy-efficient scheduling for memory-intensive GPGPU workloads

  • Author

    Seokwoo Song ; Minseok Lee ; Kim, Jung-Ho ; Woong Seo ; Yeongon Cho ; Soojung Ryu

  • Author_Institution
    KAIST, Daejeon, South Korea
  • fYear
    2014
  • fDate
    24-28 March 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    High performance for a GPGPU workload is obtained by maximizing parallelism and fully utilizing the available resources. However, this is not necessarily energy efficient, especially for memory-intensive GPGPU workloads. In this work, we propose Throttle CTA (cooperative-thread array) Scheduling (TCS) where we leverage two type of throttling - throttling the number of actives cores and throttling of warp execution in the cores - to improve energy-efficiency for memory-intensive GPGPU workloads. The algorithm requires the global CTA or thread block scheduler to reduce the number of cores with assigned thread blocks while leveraging the local warp scheduler to throttle memory requests for some of the cores to further reduce power consumption. The proposed TCS scheduling does not require off-line analysis but can be done dynamically during execution. Instead of relying on conventional metrics such as miss-per-kilo-instruction (MPKI), we leverage the memory access latency metric to determine the memory intensity of the workloads. Our evaluations show that TCS reduces energy by up to 48% (38% on average) across different memory-intensive workload while having very little impact on performance for compute-intensive workloads.
  • Keywords
    graphics processing units; low-power electronics; scheduling; MPKI; TCS; actives cores; assigned thread blocks; cooperative thread array; energy-efficient scheduling; global CTA; local warp scheduler; memory access latency metric; memory-intensive GPGPU workloads; miss-per-kilo-instruction; power consumption; thread block scheduler; throttle CTA; throttle memory requests; warp execution; Instruction sets; Kernel; Logic gates; Memory management; Monitoring; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
  • Conference_Location
    Dresden
  • Type

    conf

  • DOI
    10.7873/DATE.2014.032
  • Filename
    6800233