0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture

0.5V operation and power-gating ability of nonvolatile SRAM (NV-SRAM) cell using pseudo-spin-FinFETs (PS-FinFETs) are investigated. The cell is configured so as to achieve a minimum occupied-area design, i.e., all the FinFETs used in the cell are designed with a single fin channel. The 0.5V operations are analyzed from various static noise margins (SNMs) for the normal operation and nonvolatile power-gating (NVPG) modes. The SNMs for all the normal (hold, read, and write) operations are satisfactorily large even for the 0.5V operation, although the wordline underdrive technique is needed to be introduced for the read operation. The SNMs for the store operations of the NVPG mode also satisfy requirements for the shutdown and wake-up operations, when bias-assisted techniques are employed for the PS-FinFETs of the cell. Energy performance of the NV-SRAM cell is evaluated using break-even time (BET). A sufficiently short BET applicable to fine-grained NVPG of microprocessors and SoCs can be achieved even for the 0.5V operation with the various bias-assisted techniques. In addition, store-free shutdown architecture is further effective at reducing BET. Average power of the cell can be dramatically reduced by 0.5V operation, although the reduction rate depends on the leakage current during shutdown mode and the proportion of shutdown period. This FinFET-based NV-SRAM cell using pseudo-spin-transistor architecture is promising for NVPG of low-voltage logic systems.