• DocumentCode
    1289420
  • Title

    Impact of the vertical SOI `DELTA´ structure on planar device technology

  • Author

    Hisamoto, Digh ; Kaga, Toru ; Takeda, Eiji

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • Volume
    38
  • Issue
    6
  • fYear
    1991
  • fDate
    6/1/1991 12:00:00 AM
  • Firstpage
    1419
  • Lastpage
    1424
  • Abstract
    A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance
  • Keywords
    insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; 3D simulation; channel control; deep-submicrometer; depleted lean channel transistor; device characteristics; gate structure; high crystalline quality; high transconductance; minimized subthreshold swing; model; planar device technology; reduction in short-channel effects; selective oxidation produces; three-dimensional simulations; ultrathin SOI MOSFET; vertical SOI DELTA structure; vertical ultrathin SOI structure; Crystallization; Energy consumption; FETs; Isolation technology; Low voltage; MOSFETs; Maintenance; Oxidation; Substrates; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.81634
  • Filename
    81634