• DocumentCode
    1290204
  • Title

    Two operand binary adders with threshold logic

  • Author

    Ramos, Joseé Fernández ; Bohorquez, A.G.

  • Author_Institution
    Dept. of Electron., Malaga Univ., Spain
  • Volume
    48
  • Issue
    12
  • fYear
    1999
  • fDate
    12/1/1999 12:00:00 AM
  • Firstpage
    1324
  • Lastpage
    1337
  • Abstract
    The central topic of this paper is the implementation of binary adders with threshold logic using a new methodology that introduces two innovations: the use of the input and output carries of each bit for obtaining all the sum bits and a modification of the classic carry lookahead adder technique that allows us to obtain the expressions of the generation and propagation carries in a more appropriate way for threshold logic. In this way, it has been possible to systematize the process of design of a binary adder with threshold logic relating all its important parameters: number of bits of the operands, depth, size, maximum fan-in, and maximum weight. The results obtained are an improvement on those published to date and are summarized as follows: Depth 2 adder: s=2n, wmax=2n, fmax=2n+1. Depth 3 adder: s=4n-2[n/[√n]], wmax =2[n/[√n]], fmax=2[n/[√n]]+1. Depth d adder (asymptotic behavior): s=O(n), wmax=O(2d-1√n), fmax=O(d-1√n). If the weights are bounded by wmax:nmax=O(logd-1 wmax), d min=O(log n/log(log wmax))
  • Keywords
    adders; digital arithmetic; logic design; threshold logic; binary adders; carry lookahead adder; maximum fan-in; maximum weight; operand binary adders; threshold logic; Adders; Boolean functions; Digital arithmetic; Electronic circuits; Feedback circuits; Logic circuits; Logic design; Neural networks; Process design; Technological innovation;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.817389
  • Filename
    817389