DocumentCode
129131
Title
Equivalence checking for function pipelining in behavioral synthesis
Author
Kecheng Hao ; Ray, Sambaran ; Fei Xie
Author_Institution
Dept. of Comput. Sci., Portland State Univ., Portland, OR, USA
fYear
2014
fDate
24-28 March 2014
Firstpage
1
Lastpage
6
Abstract
Function pipelining is a key transformation in behavioral synthesis. However, synthesizing the complex pipeline logic is an error-prone process. Sequential equivalence checking (SEC) support is highly desired to provide confidence in the correctness of synthesized pipelines. However, SEC for function pipelining is challenging due to the significant difference between the behavioral specification and synthesized RTL. Furthermore, function pipelines include hardware logic for dynamically inserting “bubbles” (pipeline stalls), which bring additional difficulties in equivalence checking. We develop an SEC framework for behaviorally synthesized function pipelines by (1) building a reference pipeline model with a certified function pipelining transformation, which faithfully captures bubble insertion; and (2) checking the equivalence between the reference model and synthesized RTL. We demonstrate the scalability of our approach on industry-strength designs synthesized by a commercial tool.
Keywords
logic design; SEC framework; behavioral specification; behavioral synthesis; bubble insertion; certified function pipelining transformation; function pipelining; pipeline logic; pipeline stalls; register transfer level; sequential equivalence checking; synthesized RTL; Algorithms; Clocks; Pipeline processing; Pipelines; Registers; Schedules; Scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location
Dresden
Type
conf
DOI
10.7873/DATE.2014.163
Filename
6800364
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