A “double-face” bit-serial architecture for the 1D discrete wavelet transform

Author

Marino, Francescomaria

Author_Institution

Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy

Volume

47

Issue

1

fYear

2000

fDate

1/1/2000 12:00:00 AM

Firstpage

65

Lastpage

71

Abstract

Proposes a novel discrete wavelet transform (DWT) architecture which is fully scalable, flexible, and modular. This architecture is bit serial, and therefore, has low hardware complexity and low power requirement. Nevertheless, because of its particular structure, it operates on-the-fly (i.e., it does not require wait cycles between consecutive input samples). Moreover, a very small hardware overhead can upgrade the architecture to compute also the inverse DWT (“double-face” utilization). Hardware complexity and computing performance are analyzed in detail

Keywords

VLSI; application specific integrated circuits; computer architecture; digital signal processing chips; discrete wavelet transforms; 1D discrete wavelet transform; computing performance; double-face bit-serial architecture; flexible architecture; hardware complexity; hardware overhead; inverse DWT; modular architecture; on-the-fly operation; power requirement; scalable architecture; Adaptive signal processing; Biomedical signal processing; Computer architecture; Digital signal processing; Discrete wavelet transforms; Hardware; Performance analysis; Very large scale integration; Video signal processing; Wavelet domain;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.818896

Filename

818896