3D FPGA using high-density interconnect Monolithic Integration

Author

Turkyilmaz, O. ; Cibrario, G. ; Rozeau, O. ; Batude, P. ; Clermidy, F.

Author_Institution

CEA - LETI, Grenoble, France

fYear

2014

fDate

24-28 March 2014

Firstpage

1

Lastpage

4

Abstract

New 3D technology, called “Monolithic Integration”, offers very dense 3D interconnect capabilities. In this paper, we propose a 3D FPGA architecture with logic-on-memory approach based on this technology. The routing and computation blocks are splitted into two layers where the logic is placed on the top and memory on the bottom. Using extracted values from layout in 14nm FDSOI technology, typical benchmark circuits are evaluated in the VPR5 toolflow. The results show an area reduction of 55% compared to the 2D FPGA. More importantly, due to the lowered routing congestion, the EDP of the 3D FPGA is improved by 47%.

Keywords

field programmable gate arrays; integrated circuit interconnections; integrated logic circuits; reconfigurable architectures; silicon-on-insulator; three-dimensional integrated circuits; 2D FPGA; 3D FPGA architecture; 3D interconnect capability; EDP; FDSOI technology; VPR5 toolflow; benchmark circuits; high-density interconnect monolithic integration; logic-on-memory approach; routing congestion; size 14 nm; Computer architecture; Field programmable gate arrays; Microprocessors; Monolithic integrated circuits; Routing; Three-dimensional displays; Through-silicon vias; 3D; FPGA; monolithic integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014

Conference_Location

Dresden

Type

conf

DOI

10.7873/DATE.2014.351

Filename

6800552