Improved performance CMUT-on-CMOS devices using ALD hafnium oxide insulation layer

Higher transmit sensitivity and receive sensitivity at lower bias voltages would be achieved by CMUTs when their structure converges to an ideal parallel plate structure without an insulation layer. Using an insulation layer with high relative dielectric constant (high-K) helps achieving this goal with increased capacitance and large electric field in the vacuum gap. The effect of the insulation layer is more pronounced for high frequency, small gap CMUTs, where large pressures can be generated with smaller displacements. In this paper, we present a simple model for optimal insulation layer properties and significant improvement in both transmit and receive sensitivity by replacing the silicon nitride (Si_xN_y) insulation layer with high-K hafnium oxide (HfO₂) for a low temperature CMUT-on-CMOS process. Experiments are performed on parallel fabricated test CMUTs with 50-nm gap and 16.5-MHz center frequency to measure and compare pressure output and receive sensitivity for PECVD Si_xN_y and HfO₂ insulation layers. Results for this particular design show 6-dB improvement in receive sensitivity (V/Pa) with the collapse voltage reduced by one half. Successful CMUT-on-CMOS integration with high-k dielectric is also demonstrated.